(a) Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a field effect transistor formed on a semiconductor substrate having a piezoelectric property.
(b) Description of the Related Art
Active research has been conducted pursuing high-speed and low power LSI's which employ field effect transistors made of a III-V group compound semiconductor such as GaAs. For the development of such LSI's, a higher level of integration is required as well as miniaturization of device elements. Further, uniformity in the characteristics of device elements contained in the integrated circuits must be improved.
Conventionally, field effect transistors of the type described above are formed on a wafer so that the main surface of the wafer coincides with the (100) lattice plane of the wafer, and that drain current flows in the [011] direction, in view that the wafer is easily cleaved when chips are cut out therefrom.
However, as described in IEEE Transactions on Electron Devices, Vol. ED-31, No. 10, October, 1984, P. M. Asbeck et al., it has been known that the threshold voltage of a conventional field effect transistor varies in a case in which the field effect transistor is formed on a substrate having a piezoelectric property, such as a GaAs substrate. This is because a piezoelectric effect is induced in the substrate of the semiconductor device due to stresses in a passivation layer or an interlayer dielectric layer so that a piezoelectric charge is generated in the channel region of the field effect transistor.
In the conventional semiconductor device having field effect transistors of the type as described above, a stress generated in the dielectric layer acts to induce a piezoelectric effect in the substrate having a piezoelectric property. In other words, the gate of the field effect transistor is oriented in such a direction that piezoelectric charges are induced due to the stress. As a result, the threshold voltage shifts due to the piezoelectric charges generated in the channel region, so that the circuit may be unable to operate in a predetermined function. In addition, since a stress in the dielectric layer changes depending on the thickness of the dielectric layer, the variation of the thickness of the dielectric layer in the wafer affects the distribution of the piezoelectric charges generated in the wafer, resulting in a shift in the threshold voltage of the field effect transistor.
In an attempt to minimize a threshold voltage shift in the field effect transistor attributed to the piezoelectric effect in the dielectric layer, which is induced when the field effect transistor is formed on a GaAs substrate, Japanese Patent Laid-open Publication No. 61(1987)-88567 discloses a field effect transistor formed on a main surface of a wafer so that the plane orientation of the main surface coincides with the (N10) lattice plane of the semiconductor substrate and the direction of the drain current is parallel to the [1N0] crystal axis of the semiconductor substrate. There are no reports, however, which teach field effect transistors in which the plane orientation of the main surface of a wafer is made to coincide with a lattice plane other than the (N10) lattice plane and the gate electrode is oriented in a direction so that the drain current flows in a direction parallel to a crystal axis other than the [1N0] axis of the substrate. It is still important to enhance the flexibility in designing a semiconductor device having field effect transistors.